Define and execute verification methodologies for module to chip-level verification
Detail verification plans/reports corresponding to the circuit requirements & specifications
Implement regression tests on RTL and gate-level netlists
Support the Analog design team in mixed-signal simulations
Support the validation of the fabricated ASIC
Participate in design reviews
Write documentation in accordance with the company policy
Required
MSc / PhD in Electrical/Electronic Engineering (or related field) and 3+ years of industry experience or a BSc and 5+ years of industry experience
Solid knowledge of System Verilog for verification
Solid knowledge of a digital hardware description language and scripting languages (e.g. TCL, shell, Perl, Ruby, Python)
Experience in UVM methodology and Coverage-Driven Constrained Random functional verification is a plus
Familiar with C
Experience in UPF verification
You are a team player with critical attitude, a sense of initiative, and taking ownership and responsibility for your tasks.
Fluency in English (oral and written), min C1 level.
Greek or EU or Schengen area citizen or eligible of a valid Greek work permit
Job type: Full time
Location: Thessaloniki, Greece
Benefits of working at Thess IC
This position is intended for mid-level designers (higher levels will be considered for the ideal candidate) and carries an attractive salary. Collaboration and teamwork are highly valued, and accomplishments are duly celebrated.
Additional information
THESS IC commits to a diverse and inclusive workplace and welcomes applications from candidates willing to work in an environment that allows initiative and requires flexibility. Open time-off policy paired with a profound respect for work/life balance.
CONTACT INFO
12km Thessalonikis-Moudanion
57001, Thessaloniki
Greece
+30 2310473133
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